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INTEGRATED CIRCUITS
DATA SHEET
TDA4866 Full bridge current driven vertical deflection booster
Product specification Supersedes data of 1996 Oct 10 File under Integrated Circuits, IC02 1999 Jun 14
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
FEATURES * Fully integrated, few external components * No additional components in combination with the deflection controller TDA485x, TDA4841PS * Pre-amplifier with differential high CMRR current mode inputs * Low offsets * High linear sawtooth signal amplification * High efficient DC-coupled vertical output bridge circuit * Powerless vertical shift * High deflection frequency up to 160 Hz * Power supply and flyback supply voltage independent adjustable to optimize power consumption and flyback time * Excellent transition behaviour during flyback * Guard circuit for screen protection. QUICK REFERENCE DATA SYMBOL DC supply; note 1 VP VFB Iq Idefl Iid IFB supply voltage (pin 3) flyback supply voltage (pin 7) quiescent current (pin 7) note 2 8.2 - - - - 7 - 500 - PARAMETER CONDITIONS MIN. TYP. GENERAL DESCRIPTION
TDA4866
The TDA4866 is a power amplifier for use in 90 degree colour vertical deflection systems for frame frequencies of 50 to 160 Hz. The circuit provides a high CMRR current driven differential input. Due to the bridge configuration of the two output stages DC-coupling of the deflection coil is achieved. In conjunction with TDA485x, TDA4841PS the ICs offer an extremely advanced system solution.
MAX.
UNIT
25 60 10
V V mA
Vertical circuit deflection current (peak-to-peak value; pins 4 and 6) differential input current (peak-to-peak value) note 3 0.6 - - 2 600 A A
Flyback generator maximum current during flyback (peak-to-peak value; pin 7) 2 A
Guard circuit; note 1 V8 I8 Notes 1. Voltages refer to pin 5 (GND). 2. Up to 60 V VFB 40 V a decoupling capacitor CFB = 22 F (between pin 7 and pin 5) and a resistor RFB = 100 (between pin 7 and VFB) are required (see Fig.4). 3. Differential input current Iid = I1 - I2. guard voltage guard current guard on guard on 7.5 5 8.5 - 10 - V mA
1999 Jun 14
2
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
ORDERING INFORMATION TYPE NUMBER TDA4866 PACKAGE NAME SIL9P DESCRIPTION plastic single in-line power package; 9 leads
TDA4866
VERSION SOT131-2
BLOCK DIAGRAM
handbook, full pagewidth
GUARD output
VP
GND
VFB
8
3
5
7 FLYBACK GENERATOR
TDA4866
GUARD CIRCUIT
6 AMPLIFIER A INA 1 INPUT STAGE INB from e.g. TDA485x, TDA4841PS 2 AMPLIFIER B 4 9
OUTA CSP RSP Rp
Idefl vertical deflection coil
PROTECTION
FEEDB Rref OUTB Rm
MED750
Fig.1 Block diagram.
PINNING SYMBOL INA INB VP OUTB GND OUTA VFB GUARD FEEDB PIN 1 2 3 4 5 6 7 8 9 input A input B supply voltage output B ground output A flyback supply voltage guard output feedback input DESCRIPTION
handbook, halfpage
INA INB VP OUTB GND OUTA VFB GUARD FEEDB
1 2 3 4 5 6 7 8 9
MED751
TDA4866
Fig.2 Pin configuration.
1999 Jun 14
3
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
FUNCTIONAL DESCRIPTION The TDA4866 consists of a differential input stage, two output stages, a flyback generator, a protection circuit for the output stages and a guard circuit. Differential input stage The differential input stage has a high CMRR differential current mode input (pins 1 and 2) that results in a high electro-magnetic immunity and is especially suitable for driver units with differential (e.g. TDA485x, TDA4841PS) and single ended current signals. Driver units with voltage outputs are simply applicable as well (e.g. two additional resistors are required). The differential input stage delivers the driver signals for the output stages. Output stages The two output stages are current driven in opposite phase and operate in combination with the deflection coil in a full bridge configuration. Therefore the TDA4866 requires no external coupling capacitor (e.g. 2200 F) and operates with one supply voltage VP and a separate adjustable flyback supply voltage VFB only. The deflection current through the coil (Idefl) is measured with the resistor Rm which produces a voltage drop (Urm) of: Urm Rm x Idefl. At the feedback input (pin 9) a part of Idefl is fed back to the input stage. The feedback input has a current input characteristic which holds the differential voltage between pin 9 and the output pin 4 on zero. Therefore the feedback current (I9) through Rref is: Rm I 9 --------- x I defl R ref The input stage directly compares the driver currents into pins 1 and 2 with the feedback current I9. Any difference of this comparison leads to a more or less driver current for the output stages. The relation between the deflection current and the differential input current (Iid) is: I id Rm = I 9 --------- x I defl R ref
TDA4866
1 with Rbo 70 m and 1 - ---------------- 0.98 V U loop for Idefl = 0.7 A. The deflection current can be adjusted up to 1 A by varying Rref when Rm is fixed to 1 . High bandwidth and excellent transition behaviour is achieved due to the transimpedance principle this circuit works with. Flyback generator During flyback the flyback generator supplies the output stage A with the flyback voltage. This makes it possible to optimize power consumption (supply voltage VP) and flyback time (flyback voltage VFB). Due to the absence of a decoupling capacitor the flyback voltage is fully available. In parallel with the deflection yoke and the damping resistor (Rp) an additional RC combination (RSP; CSP) is necessary to achieve an optimized flyback behaviour. Protection The output stages are protected against: * Thermal overshoot * Short-circuit of the coil (pins 4 and 6). Guard circuit The internal guard circuit provides a blanking signal for the CRT. The guard signal is active HIGH: * At thermal overshoot * When feedback loop is out of range * During flyback. The internal guard circuit will not be activated, if the input signals on pins 1 and 2 delivered from the driver circuit are out of range or at short-circuit of the coil (pins 4 and 6). For this reason an external guard circuit can be applied to detect failures of the deflection (see Fig.6). This circuit will be activated when flyback pulses are missing, which is the indication of any abnormal operation.
Due to the feedback loop gain (VU loop) and internal bondwire resistance (Rbo) correction factors are required to determine the accurate value of Idefl: R ref 1 I defl = I id x ----------------------- x 1 - ---------------- R m + R bo V U loop
1999 Jun 14
4
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
TDA4866
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages referenced to pin 5 (GND); unless otherwise specified. SYMBOL VP VFB IFB V1, V2 I1, I2 V4, V6 I4, I6 V9 I9 V8 I8 Tstg Tamb Tj Ves Notes 1. Maximum output currents I4 and I6 are limited by current protection. 2. For VP > 13 V the guard voltage V8 is limited to 13 V. 3. Internally limited by thermal protection; switching point 150 C. 4. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-mb) PARAMETER thermal resistance from junction to mounting base VALUE 4 UNIT K/W PARAMETER supply voltage (pin 3) flyback supply voltage (pin 7) flyback supply current input voltage input current output voltage output current feedback voltage feedback current guard voltage guard current storage temperature operating ambient temperature junction temperature electrostatic handling for all pins note 3 note 4 note 2 note 1 CONDITIONS 0 0 0 0 0 0 0 0 0 0 0 -20 -20 -20 -500 MIN. MAX. 30 60 1.8 VP 5 VP 1.8 VP 5 VP + 0.4 5 +150 +75 +150 +500 V V A V mA V A V mA V mA C C C V UNIT
1999 Jun 14
5
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
TDA4866
CHARACTERISTICS VP = 15 V; Tamb = 25 C; VFB = 40 V; voltages referenced to pin 5 (GND); parameters are measured in test circuit (see Fig.3); unless otherwise specified. SYMBOL VP VFB IFB Iid(p-p) I1, 2(p-p) CMRR V1 V2 TCi,1 TCi,2 V1 - V2 I9 V9 Iid(offset) Ci INA Ci INB I4 I6 V6 V6,3 V4 V4,3 LE V4 V6 Goi Gofb Gifb PARAMETER supply voltage (pin 3) flyback supply voltage (pin 7) quiescent feedback current (pin 7) differential input current (Iid = I1 - I2) (peak-to-peak value) single ended input current (peak-to-peak value) common mode rejection ratio input clamp voltage input clamp voltage input clamp signal TC on pin 1 input clamp signal TC on pin 2 differential input voltage feedback current feedback voltage differential input offset current (Iid(offset) = I1 - I2) input capacity pin 1 referenced to GND input capacity pin 2 referenced to GND Idefl = 0; Rref = 1.5 k; Rm = 1 Iid = 0 note 2 note 3 I1 = 300 A I2 = 300 A note 1 no load; no signal CONDITIONS MIN. 8.2 VP + 6 - - 0 - 2.7 2.7 0 0 0 - 1 0 - - - - I6 = 0.7 A I6 = 1.0 A output A saturation voltage to VP output B saturation voltage to GND output B saturation voltage to VP linearity error DC output voltage DC output voltage open-loop current gain (I4, 6/Iid) open-loop current gain (I4, 6/I9) current ratio (Iid/I9) I6 = 0.7 A I6 = 1.0 A I4 = 0.7 A I4 = 1.0 A I4 = 0.7 A I4 = 1.0 A Idefl = 0.7 A; note 4 Iid = 0 A; closed-loop Iid = 0 A; closed-loop I4, 6 < 100 mA; note 5 I4, 6 < 100 mA; note 5 closed-loop - - - - - - - - - 6.6 6.6 - - - - - 7 500 300 -54 3.0 3.0 - - - 500 - - - - - - 1.3 1.6 2.3 2.7 1.3 1.6 1.0 1.3 - 7.2 7.2 100 100 -0.2 TYP. MAX. 25 60 10 600 600 - 3.3 3.3 800 800 10 600 VP - 1 20 5 5 1 1 1.5 1.8 2.9 3.3 1.5 1.8 1.6 1.9 2 7.8 7.8 - - - V V mA A A dB V V V/K V/K mV A V A pF pF UNIT
Input stage
Output stages A and B output current output current output A saturation voltage to GND A A V V V V V V V V % V V dB dB dB
1999 Jun 14
6
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
SYMBOL Idefl(ripple) PARAMETER output ripple current as a function of supply ripple CONDITIONS VP(ripple) = 0.5 V; Iid = 0; closed-loop - MIN. TYP. 1 -
TDA4866
MAX.
UNIT mA
Flyback generator V7, 6 voltage drop during flyback reverse forward V6 V6 I7 V8 V8 I8 V8 I8 V8(ext.) Notes 1. Up to 60 V VFB 40 V a decoupling capacitor CFB = 22 F (between pins 7 and 5) and a resistor RFB = 100 (between pin 7 and VFB) are required (see Fig.4). 2. Saturation voltages of output stages A and B can be increased in the event of negative input currents I1, 2 < -500 A. 3. I deflc I id D i = ---------- x -------- with Ideflc = common mode deflection current and Iidc = common mode input current. I idc I defl switching on threshold voltage switching off threshold voltage flyback current during flyback Idefl = 0.7 A Idefl = 1.0 A Idefl = 0.7 A Idefl = 1.0 A - - - - VP - 1 - -2.0 -2.3 +5.6 +5.9 - - -3.0 -3.5 +6.1 +6.5 VP + 1 1 V V V V V A
VP + 1.5 V
VP - 1.5 -
Guard circuit output voltage output voltage output current output voltage output current allowable external voltage on pin 8 VP 13 V guard on guard on; VP = 8.2 V guard on guard off guard off; V8 = 5 V 7.5 6.9 5 - 0.5 0 0 8.5 - - - 1 - - 10 - 0.4 1.5 13 V mA V mA V VP - 0.4 V
VP + 0.3 V
4. Deviation of the output slope at a constant input slope. 5. Frequency behaviour of Goi and Gofb: a) -3 dB open-loop bandwidth (-45) at 15 kHz; second pole (-135) at 1.3 MHz. b) Open-loop gain at second pole (-135) 55 dB.
1999 Jun 14
7
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
TEST AND APPLICATION INFORMATION
TDA4866
handbook, full pagewidth
I1 (A) 550 50 tI 1 from driver circuit TDA485x, TDA4841PS I1 I2 (A) 550 50 t VFB VP 1 2 3 4
TDA4866
5 6 7 8 9
Rm 1
GUARD output
6 Rref 2 k
MED752
Fig.3 Test diagram.
handbook, full pagewidth
TDA4866
1 2 3 4 5 6 7 8 9
I1 from driver circuit TDA485x, TDA4841PS I2 Vshift
25 k 10 k
Rm 1
Ldeflcoil = 5.2 mH Rdeflcoil = 4.2 CSP
(2)
GUARD output
RSP Rp
(2)
VP 220 F RFB VFB
(1) (1)
180 R ref 1.6 k
MED753
CFB 100 F (VFB < 40 V)
(1) Up to 60 V VFB 40 V, RFB = 100 and CFB = 22 F are required. (2) CSP = 10 to 330 nF and RSP = 10 to 22 are required. The value of CSP depends on minimum tflb/VFB.
Fig.4 Application diagram with driver circuit TDA485x, TDA4841PS.
1999 Jun 14
8
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
Example SYMBOL VALUE UNIT
TDA4866
Values given from application Idefl(max) Ldeflcoil Rdeflcoil Rm Rp Rref VFB Tamb Tdeflcoil Rth(j-mb) Rth(mb-amb)(1) VP tflb Ptot Pdefl PIC Rth(tot) Tj(max)(2) Notes 1. A layer of silicon grease between the mounting base and the heatsink optimizes thermal resistance. 2. Tj(max) = PIC x [Rth(j-mb) + Rth(mb-amb)] + Tamb 0.71 5.2 5.4 [= 4.2 + 7% + R()] 1 (+1%) 180 1.6 35 +50 +75 4 8 A mH k V C C K/W K/W
Calculation formula for supply voltage and power consumption Vb1 = V6, 3 + Rdeflcoil x Idefl(max) - U'L + Rm x Idefl(max) + V4 Vb2 = V6 + Rdeflcoil x Idefl(max) + U'L + Rm x Idefl(max) + V4, 3 for Vb1 > Vb2 : VP = Vb1 for Vb2 > Vb1 : VP = Vb2 with: U'L = Ldeflcoil x 2Idefl(max) x fv fv = vertical deflection frequency. I defl(max) P tot = V P x ------------------- + V P x 0.03 A + 0.1 W + V FB x I FB 2
2 1 P defl = -- ( R deflcoil + R m ) x I defl(max) 3
P IC = P tot - P defl PIC = power dissipation of the IC Pdefl = power dissipation of the deflection coil Ptot = total power dissipation. Calculation formula for flyback time (tflb) ( R deflcoil + R m ) x I defl(max) 1 + ------------------------------------------------------------------ L deflcoil V FB + V 7r - V 6r = -------------------------------- x ln ---------------------------------------------------------------------------- + t flb(off) R deflcoil + R m ( R deflcoil + R m ) x I defl(max) 1 - ------------------------------------------------------------------ V FB - ( V 7f - V 6f )
Calculated values 8.6 270 3.65 0.9 2.75 12 +83 V s W W W K/W C
t flb
with: tflb(off) = flyback switch off time = 50 s for this application (tflb(off) depends on VFB, Idefl(max), Ldeflcoil and CSP). To achieve good noise suppression the following values for Rp are recommended: Recommended values Ldeflcoil (mH) 3 6 10 15 Rp () 100 180 240 390
1999 Jun 14
9
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
TDA4866
handbook, full pagewidth
I1
driver current from TDA485x, TDA4841PS on pin 1
t
I2
driver current from TDA485x, TDA4841PS on pin 2
t V6 VFB VP
output voltage on pin 6
t
V4 VP
output voltage on pin 4
t
Idefl
deflection current through the coil
t
V8
GUARD output voltage on pin 8 during normal operation
tflb flyback time t flb depends on V FB
t
MHA062
Fig.5 Timing diagram.
1999 Jun 14
10
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
TDA4866
handbook, full pagewidth
VFB
VP 1N4448 2.2 k BC556 GUARD output HIGH = error 3.3 k BC548 22 F 220 k
MED754
TDA4866
7
6
2.2
vertical output signal
Fig.6 Application circuit for external guard signal generation.
INTERNAL PIN CONFIGURATION
book, full pagewidth
8
3
7
VP
TDA4866
6
VP
5 2 1
9
VP 4
VP
MED755
Fig.7 Internal circuits.
1999 Jun 14
11
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
PACKAGE OUTLINE SIL9P: plastic single in-line power package; 9 leads
TDA4866
SOT131-2
non-concave x Dh
D Eh
view B: mounting base side d A2
B seating plane j E
A1 b
L
c 1 Z e bp wM 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A1 max. 2.0 A2 4.6 4.2 b max. 1.1 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 2.54 Eh 6 j 3.4 3.1 L 17.2 16.5 Q 2.1 1.8 w 0.25 x 0.03 Z (1) 2.00 1.45 10 mm 9 Q
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT131-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1999 Jun 14
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA4866
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. suitable suitable(1) WAVE
1999 Jun 14
13
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
NOTES
TDA4866
1999 Jun 14
14
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection booster
NOTES
TDA4866
1999 Jun 14
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/04/pp16
Date of release: 1999 Jun 14
Document order number:
9397 750 05319

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